Third time my RAM OC became unstable within several weeks of completing stability tests. DRAM voltage is set to 1.35V. What could be the cause? | Overclock.net
JEDEC vs. Intel DDR5 specs – timings tRRD_S, tRRD_L, tFAW and tRTP in benchmark tests with Alder Lake | Page 3 | igor'sLAB